Title :
Layout modelling to predict compliance with EMC standards of power electronic converters
Author :
Podlejski, Anne-Sophie ; Breard, Arnaud ; Buttay, Cyril ; Rondon-Pinilla, Eliana ; Morel, Florent ; Vollaire, Christian
Author_Institution :
Université de Lyon - Laboratoire AMPERE (UMR CNRS 5005), 69134 Ecully Cedex, France
Abstract :
In power electronics, the layout of a converter is known to have a significant impact on its conducted emissions. This paper focuses on layout modelling in order to predict converter compliance with EMC standards before prototype manufacturing. Inductive effects and capacitive parasitic effects should be considered and models in the form of equivalent circuits are required by time domain simulators. In recent works, a software was used to obtain an equivalent circuit of the inductive effects and analytic calculations were performed to add equivalent capacitors. In this paper a single software is used to generate a model which includes both capacitive and inductive effects. The existing method and the proposed one show very similar results and fit well with experimental results. The proposed method requires less efforts and is more scalable since it can be applied to complex geometries.
Keywords :
Impedance; Integrated circuit modeling; JFETs; Layout; Semiconductor device measurement; Software; Time-domain analysis; Layout modelling; conducted emissions; power electronics;
Conference_Titel :
Electromagnetic Compatibility (EMC), 2015 IEEE International Symposium on
Conference_Location :
Dresden, Germany
Print_ISBN :
978-1-4799-6615-8
DOI :
10.1109/ISEMC.2015.7256262