Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture

Author

Dogimont, S. ; Gumm, M. ; Mombers, F. ; Mlynek, D. ; Torielli, A.

Author_Institution

Ecole Polytech. Federale de Lausanne, Switzerland

fYear

1997

fDate

14-16 Jul 1997

Firstpage

412

Lastpage

421

Abstract

In this paper, the problem of defining a high performance control structure for a parallel motion estimation architecture for MPEG2 coding is addressed. Various design and architecture choices are discussed and the final architecture is described. It represents a combined MIMD-SIMD approach which is based on a small but efficient ASIP with subword parallelism

Keywords

controllers; encoding; motion estimation; multimedia systems; parallel architectures; real-time systems; reduced instruction set computing; ASIP; MPEG2 coding; RISC CPU; combined MIMD-SIMD approach; embedded controller; high performance control structure; parallel motion estimation architecture; parallel multimedia architecture; subword parallelism; Displacement measurement; Genetics; Material storage; Motion control; Motion estimation; Reduced instruction set computing; Streaming media; Telecommunication control; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on

Conference_Location

Zurich

ISSN

2160-0511

Print_ISBN

0-8186-7959-X

Type

conf

DOI

10.1109/ASAP.1997.606846

Filename

606846