New design techniques yield low power, high resolution delta-sigma and SAR ADCS for process control, medical, seismic and battery-powered applications

Design innovation using CMOS technology has resulted in an array of new high resolution analog-to-digital converters (ADCs). New design techniques such as on-chip self-calibration have brought about more accurate successive approximation register (SAR) and delta-sigma ADCs. Three ADCs are discussed. These new chips are designed with proven CMOS processes and result in superior performance with very low power dissipation. The three A-to-D converters are: (1) 16-bit four channel DC measurement delta-sigma; (2) 16-bit self-calibrating 25 kHz SAR. (3) 24-bit variable bandwidth delta-sigma converter