Title :
Timing verification of sequential domino circuits
Author :
Van Campenhout, D. ; Mudge, T. ; Sakallah, K.A.
Author_Institution :
EECS Dept., Michigan Univ., Ann Arbor, MI, USA
Abstract :
Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An important observation is that input signals to domino gates may start changing near the end of the evaluate phase. The first method models domino gates explicitly, similar to latches. The second method treats domino gates only during pre- and post-processing steps. This method is shown to be more conservative, but easier to compute.
Keywords :
formal verification; logic testing; sequential circuits; domino gates; input signals; sequential domino circuits; static timing verification; Circuit analysis; Clocks; Computer architecture; Frequency; Laboratories; Latches; Logic; Sequential circuits; Synchronization; Timing;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569418
