Title :
Robust verification of 3D-ICs: Pros, cons and recommendations
Author :
Hogan, Matthew ; Petranovic, Dusan
Author_Institution :
Mentor Graphics, Wilsonville, OR, USA
Abstract :
A robust verification methodology for 3D-IC design is presented. This approach addresses the challenge of delivering a familiar verification solution with minimal disruption to existing design and verification flows. The proposed method provides a generic framework that allows users to specify their own 3D-IC design stacks for verification with TSVs, flip-chips or wire-bonded dies.
Keywords :
flip-chip devices; integrated circuit design; lead bonding; system-in-package; 3D IC design; TSV; flip-chips; integrated circuit design; robust verification methodology; system in package; through-silicon via; wire-bonded dies; Costs; Design methodology; Frequency; Production; Robustness; Routing; Three-dimensional integrated circuits; Through-silicon vias; Throughput; Wafer bonding; 3D-IC; IC; TSV; integrated circuits; through-silicon via; verification;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306522
