Title :
Speeding up hardware prototyping by incremental simulation/emulation
Author :
Cañellas, N. ; Moreno, J.M.
Author_Institution :
Dept. of Electron. Eng., Univ. Rovira i Virgili, Tarragona, Spain
Abstract :
We describe a method for the automatic construction of a testbench, able to dynamically communicate a standard VHDL simulator with a logic emulator by means of text files. The proposed approach significantly reduces turn-around times in an emulation based rapid system prototyping environment. In this way, time-consuming logic synthesis and technology mapping steps are moved, in the design cycle, after a previous functional verification
Keywords :
hardware description languages; logic CAD; logic simulation; virtual machines; VHDL simulator; functional verification; hardware prototyping; incremental simulation; logic emulator; logic synthesis; rapid system prototyping; technology mapping; testbench; text files; Automatic testing; Circuit simulation; Communication standards; Design engineering; Emulation; Field programmable gate arrays; Hardware; Logic testing; Prototypes; Virtual prototyping;
Conference_Titel :
Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on
Conference_Location :
Paris
Print_ISBN :
0-7695-0668-2
DOI :
10.1109/IWRSP.2000.855203
