Title :
System-level comparison of power delivery design for 2D and 3D ICs
Author :
Khan, Nauman H. ; Alam, Syed M. ; Hassoun, Soha
Author_Institution :
Dept. of Comput. Sci., Tufts Univ. Medford, Medford, MA, USA
Abstract :
Three-dimensional integrated circuits (IC) promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, render 3D power delivery design a challenge. In this paper, we provide a system-level comparison of power delivery for 2D and 3D ICs. We investigate various techniques that can impact the quality of power delivery in 3D ICs. These include through-silicon via (TSV) size and spacing, controlled collapse chip connection (C4) spacing, and a combination of dedicated and shared power delivery. Our evaluation system is composed of quad-core chip multiprocessor, memory, and accelerator engine. Each of these modules is running representative SPEC benchmark traces. Our findings are practical and provide clear guidelines for 3D power delivery optimization. More importantly, we show that it is possible to achieve 2D-like or even better power quality by increasing C4 granularity and selecting suitable TSV size and spacing.
Keywords :
integrated circuit design; microprocessor chips; power electronics; 2D IC; 3D integrated circuit; 3D power delivery design; 3D power delivery optimization; accelerator engine; asymmetrical packaging; controlled collapse chip connection spacing; quad-core chip multiprocessor; system-level comparison; through-silicon via size; through-silicon via spacing; Bonding; Copper; Dielectric substrates; Engines; Frequency; High speed integrated circuits; Integrated circuit interconnections; Integrated circuit technology; Packaging; Through-silicon vias;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306539
