Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack

To determine an appropriate cooling solution for a 3D chip stack at the design phase, it is important to estimate the total thermal resistance of a 3D chip stack by modeling correctly. It requires the parameters in the modeling to be precise (the parameter here corresponds to the thermal conductivity of each component of a 3D chip stack) and therefore precise thermal resistance measurement of each component of a 3D chip stack is necessary. A 3D chip stack is composed of interconnections, silicon substrates, back-end-of-the-line (BEOL), front-end-of-the-line (FEOL) and in this study, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. The thermal resistances of stacked chips (each chip of 730 mum thick) with the 250 mum pitch (50 mum diameter), 500 mum pitch (50 mum diameter) lead-free (SnAg) interconnections are measured and compared with the modeled results, then the thermal conductivity of SnAg interconnections is derived. The obtained the thermal conductivity of SnAg interconnections with Cu posts is 37 - 41 W/mC. The dependence of the silicon effective thermal resistance on the interconnection pitch is also studied and it is experimentally proved.