• DocumentCode
    2213498
  • Title

    High-Performance Integer Factoring with Reconfigurable Devices

  • Author

    Zimmermann, Ralf ; Güneysu, Tim ; Paar, Christof

  • Author_Institution
    Horst Gortz Inst. for IT-Security, Ruhr-Univ. Bochum, Bochum, Germany
  • fYear
    2010
  • fDate
    Aug. 31 2010-Sept. 2 2010
  • Firstpage
    83
  • Lastpage
    88
  • Abstract
    We present a novel FPGA-based implementation of the Elliptic Curve Method (ECM) for the factorization of medium-sized composite integers. More precisely, we demonstrate an ECM implementation capable to determine prime factors of up to 2,424 151-bit integers per second using a single Xilinx Virtex-4 SX35 FPGA. Using this implementation on a cluster like the COPACOBANA is beneficial for attacking cryptographic primitives like the well-known RSA cryptosystem with advanced methods such as the Number Field Sieve (NFS). To provide this vast number of integer factorizations per FPGA, we make use of the available DSP blocks on each Virtex-4 device to accelerate low-level arithmetic computations. This methodology allows the development of a time-area efficient design that runs 24 ECM cores in parallel, implementing both phase 1 and phase 2 of the ECM. Moreover, our design is fully scalable and supports composite integers in the range from 66 to 236 bits without any significant modifications to the hardware. Compared to the implementation by Gaj et al., who reported an ECM design for the same Virtex-4 platform, our improved architecture provides an advanced cost-performance ratio which is better by a factor of 37.
  • Keywords
    digital arithmetic; digital signal processing chips; field programmable gate arrays; public key cryptography; reconfigurable architectures; COPACOBANA; DSP block; FPGA; RSA cryptosystem; Xilinx Virtex-4 SX35; composite integer factorization; elliptic curve method; field programmable gate array; low level arithmetic computation; number field sieve; prime factor; reconfigurable device; COPACOBANA; Factorization; elliptic curve method; reconfigurable hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2010 International Conference on
  • Conference_Location
    Milano
  • ISSN
    1946-1488
  • Print_ISBN
    978-1-4244-7842-2
  • Type

    conf

  • DOI
    10.1109/FPL.2010.26
  • Filename
    5694225