Coprocessor synthesis of multirate system using static scheduling theory

Presents a way to perform hardware/software partitioning of multirate systems based on static priority scheduling theory. The problem is described by a set of interacting concurrent tasks. Each task is characterized by the lower bound on the time between successive arrivals of task, a deadline and a dataflow graph describing the computation to be performed on each invocation. All the tasks are implemented as threads executing on a single processor and scheduled according to a static deadline monotonic priority. All the tasks must meet their deadline. To this aim, threads may be accelerated by mapping the corresponding tasks to an associated ASIC coprocessor. The problem addressed by this paper is to reduce the coprocessor hardware cost required by the tasks to meet their deadlines. The coprocessor synthesis is modeled as a partitioning problem