Title :
Yield loss forecasting in the early phases of the VLSI design process
Author :
Heineken, Hans T. ; Khare, Jitendra ; Maly, Wojciech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data
Keywords :
VLSI; integrated circuit layout; integrated circuit modelling; integrated circuit yield; technological forecasting; VLSI design process; critical layout area; manufacturing data; metal lines; minimum spacing area; transistor density; yield loss forecasting; yield models; Analytical models; Cost function; Fabrication; Frequency; Integrated circuit modeling; Integrated circuit technology; Manufacturing; Process design; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510505
