Title :
A very high performance and manufacturable 3.3 V 0.35-μm CMOS technology for ASICs
Author :
Kizilyalli, I.C. ; Lytle, S.A. ; Jones, B.R. ; Martin, E.P. ; Shive, S.F. ; Brooks, A.L. ; Thoma, M.J. ; Schanzer, R.W. ; Sniegowski, J.W. ; Wroge, D.M. ; Key, R.W. ; Kearney, J.W. ; Stiles, K.R.
Author_Institution :
AT&T Bell Labs., Orlando, FL, USA
Abstract :
In this paper a manufacturable and high performance 0.35 μm CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 Å gate oxide, single n+-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&T´s previous generation 0.5 μm 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit technology; 0.35 micron; 3.3 V; 50 ps; 65 A; CMOS ASIC technology; Si; device scaling; high performance CMOS technology; manufacturable CMOS technology; single n+-polysilicon gate; Application specific integrated circuits; CMOS process; CMOS technology; Delay effects; Etching; Implants; MOS devices; MOSFETs; Manufacturing; Ring oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510506
