DocumentCode
2213676
Title
A proven methodology for designing one-million-gate ASICs
Author
Rincon, Ann Marie ; Trick, Michael ; Guzowski, Thomas
Author_Institution
IBM Microelectron., Essex Junction, VT, USA
fYear
1996
fDate
5-8 May 1996
Firstpage
45
Lastpage
52
Abstract
This paper describes the methodology used to design a family of ASIC chips in the 400 K to one-million-gate range in a 0.5 micron technology. Working first-pass hardware was produced at an average clock speed of 100 MHz with over 99% testability. The methodology utilized a variety of third-party CAD tools from Synopsys and Cadence in combination with proprietary IBM tools
Keywords
application specific integrated circuits; circuit CAD; design for testability; integrated circuit design; logic CAD; logic arrays; 0.5 micron; 100 MHz; ASIC design; CAD tools; Cadence; IBM tools; Synopsys; design methodology; one-million-gate ASICs; testability; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Clocks; Delay; Design for testability; Design methodology; Process design; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location
San Diego, CA
Print_ISBN
0-7803-3117-6
Type
conf
DOI
10.1109/CICC.1996.510509
Filename
510509
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