Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing

We discuss aspects of low temperature processing relating to the formation of through-silicon vias [TSV] for 3D-IC applications. An optimized deep silicon etch process produces 10:1 aspect ratio vias with scallop size less than 50 nm and with minimal bow and sidewall roughness. Emphasis is given to a low temperature [ges150degC] PECVD dielectric liner deposition process which produces stable, low leakage films with high conformality. Finally, aspects of barrier-seed metallization are discussed and fully metalized vias are shown.