A high-speed low-power 0.3 μm CMOS gate array with variable threshold voltage (VT) scheme

Author

Kuroda, Tadahiro ; Fujita, Tetsuya ; Nagamatu, Tetsu ; Yoshioka, Shinichi ; Sei, Toshikazu ; Matsuo, Kenji ; Hamura, Y. ; Mori, Toshiaki ; Murota, Masayuki ; Kakumu, Masakazu ; Sakurai, Takayasw

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1996

fDate

5-8 May 1996

Firstpage

53

Lastpage

56

Abstract

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3 μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance

Keywords

CMOS logic circuits; integrated circuit design; logic design; 0.3 micron; CMOS gate array; high-speed low-power gate array; low standby power dissipation; variable threshold voltage scheme; Amplitude modulation; CMOS technology; Leakage current; Monitoring; Power dissipation; Power supplies; Semiconductor devices; Switches; Switching circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510510

Filename

510510