Title :
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
Author :
Chen, C.L. ; Yost, D.-R. ; Knecht, J.M. ; Chapman, D.C. ; Oakley, D.C. ; Mahoney, L.J. ; Donnelly, J.P. ; Soares, A.M. ; Suntharalingam, V. ; Berger, R. ; Bolkhovsky, V. ; Hu, W. ; Wheeler, B.D. ; Keast, C.L. ; Shaver, D.C.
Author_Institution :
Lincoln Lab., Massachusetts Inst. of Technol., Lincoln, MA, USA
Abstract :
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 times 1024 diode array with 8-mum pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
Keywords :
III-V semiconductors; gallium arsenide; image sensors; indium compounds; readout electronics; sensor arrays; silicon-on-insulator; 3D vias; InGaAs; InP; SOI wafer; Si readout circuits; diode array; hybridize InP-based image sensor arrays; silicon-on-insulator readout circuits; size 150 mm; wafer-scale 3D integration; Diodes; Fabrication; III-V semiconductor materials; Image sensors; Indium gallium arsenide; Indium phosphide; Integrated circuit interconnections; Sensor arrays; Silicon on insulator technology; Wafer bonding;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306556
