A pipelined digital differential matched filter FPGA implementation and VLSI design

A digital matched filter having a differential and pipelined structure is proposed for CDMA (Code Division Multiple Access) communication systems. A novel differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summation (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves half of the hardware and power, but also improves the speed to a single operation time of M&S. These features make the PDDMF more suitable for personal communication high speed and low power requirements than the conventional methods. The FPGA of the DDMF (Digital Differential Matched Filter) verifies the matched filter using the proposed differential PN code scheme. Moreover, a 64 taps length PDDMF with 4 bits soft decision using 5 V 0.8 μm CMOS standard cells is designed. The active chip area is 2.6×2.6 mm². Simulation results demonstrate that the chip rate of the PN code in the PDDMF can achieve 45 M chips/sec