Title :
A pipelined digital differential matched filter FPGA implementation and VLSI design
Author :
Liu, Kuang-Chan ; Lin, Wun-Chang ; Wang, Chorng-Kuang
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
A digital matched filter having a differential and pipelined structure is proposed for CDMA (Code Division Multiple Access) communication systems. A novel differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summation (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves half of the hardware and power, but also improves the speed to a single operation time of M&S. These features make the PDDMF more suitable for personal communication high speed and low power requirements than the conventional methods. The FPGA of the DDMF (Digital Differential Matched Filter) verifies the matched filter using the proposed differential PN code scheme. Moreover, a 64 taps length PDDMF with 4 bits soft decision using 5 V 0.8 μm CMOS standard cells is designed. The active chip area is 2.6×2.6 mm2. Simulation results demonstrate that the chip rate of the PN code in the PDDMF can achieve 45 M chips/sec
Keywords :
CMOS digital integrated circuits; VLSI; code division multiple access; digital filters; field programmable gate arrays; integrated circuit design; matched filters; pipeline arithmetic; pseudonoise codes; 0.8 micron; 5 V; CDMA communication systems; FPGA implementation; VLSI design; code division multiple acess; differential PN code scheme; low power requirements; pipelined digital differential matched filter; pseudo-noise code scheme; Application specific integrated circuits; Broadcasting; Energy consumption; Field programmable gate arrays; Hardware; Matched filters; Multiaccess communication; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510515
