Title :
3D integration technology for set-top box application
Author :
Henry, D. ; Cheramy, S. ; Charbonnier, J. ; Chausse, P. ; Neyret, M. ; Manquat, C. Brunet ; Verrun, S. ; Sillon, N. ; Bonnot, L. ; Gagnard, X. ; Saugier, E.
Author_Institution :
CEA Leti - MINATEC, Grenoble, France
Abstract :
In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer. This flow needed to develop specific wafer level packaging technologies such as: (1) Top chip & bottom chip interconnections (2) High aspect ratio TSV included into the bottom wafer (3) Backside interconnections for subsequent packaging step (4) Temporary bonding and debonding of bottom wafer (5) Top chip stacking on bottom wafer. The complete process flow will be presented. Then, a technical focus will be done on the backside interconnections step. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed.
Keywords :
integrated circuit interconnections; wafer level packaging; 3D integration technology; backside interconnections; bottom chip interconnections; set top box demonstrator; set-top box application; top chip interconnections; wafer level packaging; Copper; Packaging; Sawing; Silicon; Stacking; Testing; Through-silicon vias; Vehicles; Wafer bonding; Wafer scale integration; Stacking-back side connections; Trough Silicon Vias (TSV); Wafer level Packaging;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306561
