• DocumentCode
    2214022
  • Title

    Test Compression for Dynamically Reconfigurable Processors

  • Author

    Inoue, H. ; Yamada, Junya ; Yoneda, Hideyuki ; Togawa, Katsumi ; Furuta, Koichiro

  • Author_Institution
    NEC Corp. & Renesas Electron., Kawasaki, Japan
  • fYear
    2010
  • fDate
    Aug. 31 2010-Sept. 2 2010
  • Firstpage
    205
  • Lastpage
    210
  • Abstract
    We present the world´s first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.
  • Keywords
    multiprocessing systems; reconfigurable architectures; dynamically reconfigurable processor; test compression technique; test time reduction; DRP; component; double pattern compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2010 International Conference on
  • Conference_Location
    Milano
  • ISSN
    1946-1488
  • Print_ISBN
    978-1-4244-7842-2
  • Type

    conf

  • DOI
    10.1109/FPL.2010.49
  • Filename
    5694248
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2214022