DocumentCode
2214090
Title
A 0.9 V, 4 K SRAM for embedded applications
Author
Caravella, James S.
Author_Institution
Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
fYear
1996
fDate
5-8 May 1996
Firstpage
119
Lastpage
122
Abstract
A 4 Kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 volts with a RMS run power (1 MHz) of 22 μW. The circuit operates at maximum frequency of 38 MHz at a supply voltage of 1.6 volts with a RMS run power (1 MHz) of 32 μW. The design utilizes a sub-blocked array architecture as well as selective use of NOR/NAND based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power
Keywords
CMOS memory circuits; NAND circuits; NOR circuits; SRAM chips; cellular arrays; integrated circuit design; memory architecture; 0.9 V; 1.6 V; 12 MHz; 22 muW; 32 muW; 38 MHz; 4 Kbit; CMOS; NOR/NAND based decode logic; RMS run power; SRAM; embedded applications; functionality; glitch-free design; sense amplifier design; sub-blocked array architecture; supply voltage; Batteries; CMOS logic circuits; CMOS technology; Energy consumption; Equations; Frequency; Logic arrays; Product design; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location
San Diego, CA
Print_ISBN
0-7803-3117-6
Type
conf
DOI
10.1109/CICC.1996.510525
Filename
510525
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