Title :
A self clocked FPGA for general purpose logic emulation
Author_Institution :
Inf. Syst. Lab., Stanford Univ., CA, USA
Abstract :
This paper describes the architecture of an entirely self-clocked FPGA. Such an FPGA would avoid clock distribution problems, facilitate circuit composition and increase the amount of hardware concurrency, as well as reliably operate at its maximum speed without timing analysis. These unique advantages would be of great use in many functional simulation and logic emulation applications targeting larger designs requiring many FPGAs
Keywords :
circuit analysis computing; clocks; digital simulation; field programmable gate arrays; logic CAD; circuit composition; clock distribution; functional simulation; general purpose logic emulation; hardware concurrency; logic emulation; self clocked FPGA; Circuits; Clocks; Delay; Design automation; Emulation; Field programmable gate arrays; Hardware; Logic; Routing; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510531
