Title :
Gate stack technology for nanoscale devices
Author :
Lee, Byoung Hun ; Kirsch, Paul ; Song, Seungchul ; Choi, Rino ; Jammy, Rajarao
Author_Institution :
SEMATECH, Austin
Abstract :
The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Si-based devices.
Keywords :
CMOS integrated circuits; dielectric materials; nanotechnology; silicon; gate stack technology; nanoscale devices; non-silicon-based devices; scaled nanoscale CMOS devices; silicon devices; CMOS technology; Electrodes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Jamming; Nanoscale devices; Silicon devices; Technological innovation; Tunneling; gate stack; high transport channel; high-k dielectrics;
Conference_Titel :
Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE
Conference_Location :
Gyeongju
Print_ISBN :
978-1-4244-0541-1
Electronic_ISBN :
978-1-4244-0541-1
DOI :
10.1109/NMDC.2006.4388841
