Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

Author

Yun, J.G. ; Kim, Y. ; Park, I.H. ; Cho, S.J. ; Lee, J.H. ; Kim, D.H. ; Lee, G.S. ; Song, J.Y. ; Lee, J.D. ; Park, B.G.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul

Volume

1

fYear

2006

fDate

22-25 Oct. 2006

Firstpage

214

Lastpage

215

Abstract

Investigation of 4-bit SONOS nonvolatile memory with 3-dimensional structure has been done using a 3-dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Si-fin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient V_THmiddot window margin of 2 V.

Keywords

elemental semiconductors; numerical analysis; semiconductor device models; semiconductor storage; semiconductor-insulator-semiconductor devices; silicon; silicon compounds; 3-dimensional numerical simulation; SONOS nonvolatile memory; Si-SiO₂-SiN-SiO₂-Si; Si-SiO₂-SiN-SiO₂-Si - Interface; channel length; silicon-oxide-nitride-oxide-silicon devices; voltage 2 V; word length 4 bit; Computer science; Couplings; Electrons; Interference; Nonvolatile memory; Numerical simulation; SONOS devices; Threshold voltage; 3-dimensional numerical simulation; 3-dimensional structure; 4-bit SONOS device; VTH window;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE

Conference_Location

Gyeongju

Print_ISBN

978-1-4244-0540-4

Electronic_ISBN

978-1-4244-0541-1

Type

conf

DOI

10.1109/NMDC.2006.4388845

Filename

4388845