A high density embedded array programmable logic architecture

Author

Reddy, Srinivas ; Cliff, Richard ; Jefferson, D. ; Lane, Christopher ; Sung, C.K. ; Wang, Bonnie ; Huang, Joseph ; Chang, Wanli ; Cope, Todd ; McClintock, Cameron ; Leong, William ; Ahanin, Bahram ; Turner, John

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

1996

fDate

5-8 May 1996

Firstpage

251

Lastpage

254

Abstract

An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates

Keywords

integrated circuit interconnections; integrated circuit layout; logic design; network routing; programmable logic arrays; timing; FIFOs; PLA; SRAM based logic architecture; high density embedded array architecture; megafunctions; microprocessors; multidimensional interconnect scheme; multipliers; programmable logic architecture; Computer architecture; Integrated circuit interconnections; Logic arrays; Logic devices; Logic programming; Programmable logic arrays; Reconfigurable logic; Registers; Routing; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510553

Filename

510553