Title :
The architecture and test structures of the XC8100 FPGA family
Author :
Fawcett, B. ; Goetting, E. ; Schultz, D. ; Parlour, D. ; Frake, S. ; Costello, P. ; Eccles, R. ; Leone, B. ; Marquez, D. ; Stokes, S. ; Palczewski, M. ; Peterson, W. ; Gannon, T. ; Hart, W. ; Look, K. ; Voogel, M. ; West, G. ; Tong, V. ; Chang, A. ; Chung
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
The XC8100 FPGA family is based on a new metal-to-metal antifuse technology and a “sea-of-gates” type architecture. Programmable interconnect elements are stacked vertically between metal layers and above the fine-grained logic cells, resulting in small die sizes and low cost. The basic cell is designed specifically for technology-independent design. Each cell can be configured to implement combinatorial, sequential, or three-state buffering functions. Other architectural features include a flexible set of high-drive buffers, output slew rate controls, and PCI-compatible I/O structures. A patented programming and test structure addresses the problem of providing for 100% post-program verification without test vectors
Keywords :
CMOS logic circuits; field programmable gate arrays; integrated circuit testing; logic testing; PCI-compatible I/O structures; SOG architecture; XC8100 FPGA family; combinatorial functions; high-drive buffers; metal-to-metal antifuse technology; output slew rate controls; post-program verification; programmable interconnect elements; sea-of-gates architecture; sequential functions; technology-independent design; test structure; three-state buffering functions; CMOS logic circuits; Circuit testing; Costs; Field programmable gate arrays; Integrated circuit interconnections; Logic programming; Logic testing; Programmable logic arrays; Routing; Silicon;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510554
