Biologically inspired image sensor/processor architecture with 2D cellular neural network for vision

Author

Cho, Kwang-Bo ; Sheu, Bing J. ; Young, Wayne C.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

1

fYear

1998

fDate

4-8 May 1998

Firstpage

569

Abstract

A scalable image sensor array processor with frame memory buffer and cellular neural network (CNN) for nearest neighbor interaction has been developed in a 0.5 μm HP CMOS technology. The CNN with analog programmable weights was constructed with compact mixed-signal VLSI circuit components in the current-mode techniques. The low voltage, low power operation is supported with the current mode scheme which scales well with the supply voltage. VLSI design of a variable gain neuron circuit can be incorporated into the prototype to realize the optimal solution capability using hardware annealing

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; cellular neural nets; image sensors; neural chips; CMOS IC; VLSI; analog programmable weights; cellular neural network; current-mode; frame memory buffer; hardware annealing; nearest neighbor interaction; scalable image sensor array processor; CMOS image sensors; CMOS process; CMOS technology; Cellular neural networks; Circuits; Image sensors; Low voltage; Nearest neighbor searches; Sensor arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on

Conference_Location

Anchorage, AK

ISSN

1098-7576

Print_ISBN

0-7803-4859-1

Type

conf

DOI

10.1109/IJCNN.1998.682330

Filename

682330