• DocumentCode
    2215336
  • Title

    Dynamically Reconfigurable Vision-Chip Architecture

  • Author

    Yasuda, Maki ; Watanabe, Minoru

  • Author_Institution
    Electr. & Electron. Eng., Shizuoka Univ., Hamamatsu, Japan
  • fYear
    2010
  • fDate
    Aug. 31 2010-Sept. 2 2010
  • Firstpage
    508
  • Lastpage
    512
  • Abstract
    Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported.
  • Keywords
    image recognition; real-time systems; reconfigurable architectures; robots; analog-type vision chips; autonomous vehicles; digital vision chips; real-time image recognition; reconfigurable vision-chip architecture; robots; Dynamically reconfigurable devices; Field Programmable Gate Arrays; Vision chips;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2010 International Conference on
  • Conference_Location
    Milano
  • ISSN
    1946-1488
  • Print_ISBN
    978-1-4244-7842-2
  • Type

    conf

  • DOI
    10.1109/FPL.2010.101
  • Filename
    5694302