Title :
A 36 MHz CMOS fixed-point G.728 low delay CELP integrated decoder-encoder
Author :
Soon, William Bong Hock ; Goyal, Sameer ; Hsu, Liu Chong ; Wee, Yeo Lik
Author_Institution :
Siemens Components Pte Ltd., Singapore
Abstract :
The highly integrated JADE (Joint Audio Decoder-Encoder) device implements audio compression using either G.711, G.722 or G.728 compression algorithms. The integration of peripherals, interfaces and memories with a fixed point DSP (digital signal processor) to implement complex speech algorithms such as G.728, opens up the market for low cost digital telecommunications applications. Using the G.728 Low Delay Code Excited Linear Prediction (LD-CELP) algorithm, the device compresses/decompresses a digitized PCM (64 kbps) or linear (128 kbps) voice signal to/from a 16 kbps bit stream. The device has been fabricated in a 0.5 μm n-well CMOS process
Keywords :
CMOS digital integrated circuits; audio coding; delays; digital arithmetic; digital signal processing chips; linear predictive coding; speech codecs; speech coding; telecommunication computing; 0.5 micron; 128 kbit/s; 16 kbit/s; 36 MHz; 64 kbit/s; CELP integrated decoder-encoder; CMOS IC; G.728 compression algorithm; JADE device; audio compression; code excited linear prediction; complex speech algorithms; decompression; digital signal processor; digitized PCM voice signal; fixed-point DSP chip; joint audio decoder-encoder device; linear voice signal; low cost digital telecommunications applications; low delay type; n-well CMOS process; Audio compression; Compression algorithms; Costs; Decoding; Delay lines; Digital signal processing; Digital signal processors; Prediction algorithms; Signal processing algorithms; Speech processing;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510577
