DocumentCode
2215396
Title
A 1.8 V 36 mW DSP for the half-rate speech codec
Author
Shiraishi, Taketora ; Kawamoto, Koji ; Ishikawa, Kazuyuki ; Sato, Hisakazu ; Asai, Fumiyasu ; Teraoka, Eiichi ; Kengaku, Toru ; Takata, Hidehiro ; Tokuda, Takeshi ; Nishida, Kouichi ; Saitoh, Kazunori
Author_Institution
Mitsubishi Electr. Corp., Hyogo, Japan
fYear
1996
fDate
5-8 May 1996
Firstpage
371
Lastpage
374
Abstract
A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V
Keywords
CMOS digital integrated circuits; digital signal processing chips; linear predictive coding; speech codecs; speech coding; 1.8 V; 16 bit; 36 mW; dual datapath architecture; half-rate speech codec; low bit-rate speech processing; low-power DSP chip; low-power circuit design techniques; power consumption; Circuit synthesis; Digital signal processing; Energy consumption; Finite impulse response filter; Prediction algorithms; Random access memory; Read only memory; Registers; Speech codecs; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location
San Diego, CA
Print_ISBN
0-7803-3117-6
Type
conf
DOI
10.1109/CICC.1996.510578
Filename
510578
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