A three-layer router for standard cell VLSI circuits

Author

Tsui, Raymond Y. ; Shenoy, Allan P. ; Tampone, Joanne ; Taylor, Susan L.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

fYear

1988

fDate

7-9 Jun 1988

Firstpage

1441

Abstract

The authors present a three-layer router for standard cell VLSI circuits using two-layer metal technology. This router has three steps: feedthrough generation, loose routing, and channel routing. A novel feedthrough model taking advantage of the second metal layer for routing is proposed. The strategy of a feedthrough grid pattern that facilitates clock skew minimization and critical signal routing is also described. A clock skew minimization scheme based on this strategy has been incorporated into the existing loose router. Comparisons between single-layer metal and two-layer metal designs in terms of chip area and circuit performance are given. With this three-layer routing strategy, chip area reduction of 20-30% and significant circuit performance improvements have been achieved

Keywords

VLSI; application specific integrated circuits; cellular arrays; circuit layout CAD; logic CAD; channel routing; chip area; circuit performance; circuit performance improvements; clock skew minimization; critical signal routing; feedthrough generation; feedthrough grid pattern; loose routing; standard cell VLSI circuits; three-layer router; two-layer metal technology; Circuit optimization; Clocks; Geometry; Libraries; Mesh generation; Minimization; Production systems; Routing; Semiconductor process modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo

Type

conf

DOI

10.1109/ISCAS.1988.15200

Filename

15200