• DocumentCode
    2215489
  • Title

    Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell

  • Author

    Song, Seung-Hyun ; Lee, Jeong-Soo ; Jeong, Yoon-Ha

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang
  • Volume
    1
  • fYear
    2006
  • fDate
    22-25 Oct. 2006
  • Firstpage
    512
  • Lastpage
    513
  • Abstract
    A vertical channel nanoscale MOSFET for low leakage dynamic random access memory (DRAM) cell is proposed. Due to longer channel length than that of the conventional planner structure, the vertical channel structure can dramatically reduce short channel effect (SCE). This structure features a source extension to enhance subthreshold swing (SS), and a neck sidewall spacer to reduce gate induced drain leakage (GIDL).
  • Keywords
    DRAM chips; MOSFET; dynamic random access memory; gate induced drain leakage; low leakage DRAM cell; planner structure; short channel effect; subthreshold swing; vertical channel nanoscale MOSFET; Costs; DRAM chips; Degradation; Implants; Lithography; MOSFETs; Nanostructures; Neck; Production; Random access memory; DRAM; MOSFETs; Vertical channel;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE
  • Conference_Location
    Gyeongju
  • Print_ISBN
    978-1-4244-0540-4
  • Electronic_ISBN
    978-1-4244-0541-1
  • Type

    conf

  • DOI
    10.1109/NMDC.2006.4388879
  • Filename
    4388879
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2215489