Title :
Exploiting locality for low-power design
Author :
Mehra, Renu ; Guerra, Lisa ; Rabney, J.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
We propose a new high-level synthesis technique for the low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexers and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexer power of 62.9% and 38.5%, respectively, resulting in an average reduction of 18.5% in total power
Keywords :
circuit CAD; circuit layout CAD; high level synthesis; integrated circuit design; real-time systems; algorithm partitioning; compact layouts; high-level synthesis technique; locality; low-power design; real-time applications; Application software; Clustering algorithms; Design optimization; Energy consumption; Filters; Hardware; High level synthesis; Partitioning algorithms; Resource management; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510585