DocumentCode
2215628
Title
An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecture
Author
Nagaraj, K. ; Fetterman, H.S. ; Shariatdoust, R.S. ; Anidjar, J. ; Lewis, S.H. ; Alsayegh, J. ; Renninger, R.G.
Author_Institution
AT&T Bell Labs., Allentown, PA, USA
fYear
1996
fDate
5-8 May 1996
Firstpage
423
Lastpage
426
Abstract
An efficient architecture for a pipelined A/D converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter is realized using just 3 amplifiers (instead of 7 amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a sampling rate of over 50 Msamples/s has been achieved in a 0.9-μm CMOS technology
Keywords
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.9 micron; 8 bit; ADC; CMOS technology; area-efficient architecture; pipelined A/D converter; power-efficient architecture; Arithmetic; CMOS technology; Capacitors; Circuits; Image storage; Operational amplifiers; Pipelines; Power dissipation; Redundancy; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location
San Diego, CA
Print_ISBN
0-7803-3117-6
Type
conf
DOI
10.1109/CICC.1996.510589
Filename
510589
Link To Document