Fair Dynamic Pipelining Memory Access Scheduling

Technology trends are leading to increasing number of cores on chip. All these cores inherently share the DRAM bandwidth. The on-chip and off-chip cache or memory resources are limited and in many situations, cannot hold the working set of the threads running on all these cores. This situation makes DRAM bandwidth a critical shared resource. Hence computer designers are faced with an increasing Processor - Memory Performance Gap, which now is the primary obstacle to improved computer system performance. Existing DRAM access management schemes provide support for enforcing bandwidth shares but have problems like starvation, complexity, and unpredictable DRAM access latency. In this paper, we propose a DRAM access management scheme - Fair Dynamic Pipelining (FDP) memory access scheduling with two key features. First, the scheme avoids unexpected long latencies or starvation of memory requests using the dynamic pipeline arrangement policy. Second, it provides an alterable priority strategy to make the response of memory more fairly. The experiment result shown that the FDP scheduling makes the bandwidth shares to achieve desired average latencies for multi cores memory accesses.