[Title page i]

fYear

2010

fDate

Aug. 31 2010-Sept. 2 2010

Abstract

The following topics are dealt with: FPGA; reconfigurable array; RISC core; FPGA architecture; multimedia; random number; cryptography; multithreading architecture; multicore system; GPU; CPU; graphics processing unit; reconfigurable architecture; self-aware adaptation; NoC; networks-on-chip; SoC; FPGA design; rapid prototyping; embedded systems; DSP; fault detection; fault diagnostics; high level language; hardware compilation; and floating point multiplier.

Keywords

coprocessors; cryptography; digital signal processing chips; embedded systems; fault diagnosis; field programmable gate arrays; floating point arithmetic; high level languages; logic design; multi-threading; multimedia systems; multiplying circuits; multiprocessing systems; random number generation; reconfigurable architectures; reduced instruction set computing; software prototyping; system-on-chip; CPU; DSP; FPGA; FPGA design; GPU; NoC; RISC core; SoC; cryptography; embedded systems; fault detection; fault diagnostics; field programmable gate array; floating point multiplier; graphics processing unit; hardware compilation; high level language; multicore system; multimedia; multithreading architecture; networks-on-chip; random number; rapid prototyping; reconfigurable architecture; reconfigurable array; self-aware adaptation;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications (FPL), 2010 International Conference on

Conference_Location

Milano

ISSN

1946-1488

Print_ISBN

978-1-4244-7842-2

Type

conf

DOI

10.1109/FPL.2010.1

Filename

5694323