DocumentCode :
2215813
Title :
Removing user-specified false paths from timing graphs
Author :
Blaauw, David ; Panda, Rajendran ; Das, Abhijit
Author_Institution :
Motorola, Inc.
fYear :
2000
fDate :
2000
Firstpage :
270
Lastpage :
273
Keywords :
Circuit analysis; Circuit optimization; Constraint optimization; Design optimization; Digital integrated circuits; Latches; Logic circuits; Performance analysis; Permission; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
Type :
conf
DOI :
10.1109/DAC.2000.855317
Filename :
855317
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2215813
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