Polynomial evaluation on multimedia processors

Author

Villalba, Julio ; Bandera, Gerardo ; Gonzalez, Mario A. ; Hormigo, Ja Vier ; Zapata, Emilio L.

Author_Institution

Comput. Archit. Dept., Malaga Univ., Spain

fYear

2002

fDate

2002

Firstpage

265

Lastpage

274

Abstract

In this paper we deal with polynomial evaluation based on new processor architectures for multimedia applications. We introduce some algorithms to take advantage of the new attributes of multimedia processors, such as VLIW (very long instruction word) and SIMD (single instruction multiple data architecture) architectures. Algorithms to support polynomial evaluation based only in addition/shift operations and other different algorithms with MAC (multiply-and-add) instructions are analyzed and tailored to subword parallelism units of the new processors. Both potential instruction-level and machine-level parallelism are fully exploited through concurrent use of all functional units.

Keywords

digital signal processing chips; instruction sets; microprocessor chips; multimedia computing; parallel algorithms; parallel architectures; polynomials; MAC instructions; SIMD; VLIW; addition/shift operations; digital signal processing; functional unit concurrent use; instruction-level parallelism; machine-level parallelism; multimedia extensions; multimedia processor polynomial evaluation algorithms; multiply-and-add instructions; processor architecture; single instruction multiple data architecture; subword parallelism units; very long instruction word architecture; Polynomials;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on

ISSN

2160-0511

Print_ISBN

0-7695-1712-9

Type

conf

DOI

10.1109/ASAP.2002.1030725

Filename

1030725