Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter

Author

Lu, Chih-Chung ; Tseng, Shau-Yin

Author_Institution

Internet Platform Application Dept., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2002

fDate

2002

Firstpage

277

Lastpage

285

Abstract

This paper proposed a method of integrating the AES encrypter and the AES decrypter into a full functional AES crypto-engine. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv)SubBytes module and (Inv)Mixcolumns module, etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart cards, PDAs, and mobile phones, etc.

Keywords

cryptography; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; mobile handsets; notebook computers; smart cards; standards; AES crypto-engine; AES decryption; AES encrypter/decrypter integrated design; AES encryption; Advanced Encryption Standard; InvMixcolumns module; InvSubBytes module; Mixcolumns module; PDA; SubBytes module; hardware-critical applications; high data rate architecture; low-complexity architecture; mobile phones; reduced hardware resource requirements; smart cards; Application software; Communication standards; Computer architecture; Cryptography; Data security; Design optimization; Hardware; Internet; NIST; Smart cards;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on

ISSN

2160-0511

Print_ISBN

0-7695-1712-9

Type

conf

DOI

10.1109/ASAP.2002.1030726

Filename

1030726