Title :
Over an order of magnitude DRAM test time reduction by charge offset
Author :
Hashimoto, Masashi ; Uchida, Isao ; Hatakoshi, Seishi
Author_Institution :
Texas Instrum. Japan Ltd, Ibaraki, Japan
Abstract :
A circuit technique of reducing DRAM data retention test time by over an order of magnitude is described. The circuit requires almost zero area overhead. Data retention test time reduction is achieved by using a charge offset realized by manipulating a dummy cell reference voltage. The retention time parallel shift in logarithmic time domain with respect to charge offset was confirmed experimentally. Overall DRAM test time can be reduced by 2/3 since this amount of time is being utilized to perform the data retention test
Keywords :
DRAM chips; integrated circuit testing; DRAM test time reduction; charge offset; circuit technique; data retention test; dummy cell reference voltage; dynamic RAM; Circuit testing; Data engineering; Design engineering; Instruments; Logic; MOS capacitors; Performance evaluation; Random access memory; Silicon; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510602
