DocumentCode
2216106
Title
Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS
Author
Currie, Steven M. ; Schumacher, Paul R. ; Gilbert, Barry K. ; Swartzlander, Earl E. ; Randall, Barbara A.
Author_Institution
Mayo Found., Rochester, MN, USA
fYear
2002
fDate
2002
Firstpage
335
Lastpage
343
Abstract
The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 μm bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.
Keywords
CMOS digital integrated circuits; SRAM chips; application specific integrated circuits; computer interfaces; digital signal processing chips; fast Fourier transforms; integrated circuit design; integrated circuit testing; logic CAD; pipeline processing; 0.25 micron; 10 mm; 16 bit; 3.3 V; 5 V; Mayo FFT processor; SRAM; bulk CMOS technology; command driven interface; complex fast Fourier transform ASIC; distributed register banks; high voltage tolerant I/O; intermediate calculation storage; maximum flexibility design; overflow correction circuitry; overflow detection; power-of-two-sized transforms; radix-2 FFT processor; real/imaginary samples; redundant computation modules; single chip CMOS 1D FFT pipelined ASIC; static RAM; user programmable sine/cosine coefficient storage; user programmable transform length; user selected transform point size; user-selectable operand scaling; Application specific integrated circuits; CMOS technology; Clocks; Computer architecture; Computer interfaces; Design engineering; Distributed computing; Fast Fourier transforms; Pipelines; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on
ISSN
2160-0511
Print_ISBN
0-7695-1712-9
Type
conf
DOI
10.1109/ASAP.2002.1030732
Filename
1030732
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