Design and implementation of a 1024-point pipeline FFT processor

Author

He, Shousheng ; Torkelson, Mats

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

fYear

1998

fDate

11-14 May 1998

Firstpage

131

Lastpage

134

Abstract

The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-2² algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm². With 3.3 V power supply, it can compute 2ⁿ, n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; pipeline processing; 0.5 micron; 1024-point FFT processor; 3.3 V; 30 MHz; CMOS technology; VLSI implementation; complex multipliers; complex-word data memory; inverse FFT; pipeline FFT processor; radix-2² algorithm; Arithmetic; CMOS technology; Clocks; Computer architecture; Delay; Hardware design languages; OFDM; Pipelines; Sampling methods; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694922

Filename

694922