Title :
Gate-array library design using local interconnect
Author :
Wissel, Larry ; Stout, Douglas ; Buck, Nathan
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
An ASIC gate-array library has been created in 0.4 μm CMOS technology using a local interconnect level. The gate-array cells in this library are denser than their counterparts in a library without local interconnect. The comparison of two benchmarks, including a 520K-gate ASIC routed with both libraries, further shows that the local interconnect allows higher density of ASIC designs due to more efficient use of the global inter-connect layers
Keywords :
CMOS logic circuits; application specific integrated circuits; circuit layout CAD; integrated circuit interconnections; logic CAD; logic arrays; network routing; 0.4 micron; ASIC; CMOS technology; benchmarks; gate-array library design; global interconnect layers; local interconnect; network routing; Application specific integrated circuits; CMOS technology; Diodes; Foundries; Integrated circuit interconnections; Libraries; Microelectronics; Robustness; Routing; Tungsten;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510608
