A 3 GigaHertz 4:1 time division multiplexer with output retiming

Author

Flower, Graham

Author_Institution

Hewlett Packard, San Jose, CA, USA

fYear

1988

fDate

12-13 Sep 1988

Firstpage

146

Lastpage

149

Abstract

A 3 GHz 4:1 multiplexer has been designed in Hewlett Packard´s newest bipolar process. The circuit is fully differential and uses ECL-level outputs. Inputs are also ECL levels. The design uses a travelling wave divider approach to generate the timing signals for a 4:1 series gated asynchronous multiplexer. An output flip-flop and an inverting (on-chip) delay line are used in conjunction to retime the output data. The chip operates to 3 GHz from ~100 MHz with a power dissipation of 1.8 W. Off-chip drivers are on chip terminated to approximately 100 Ω to present a VSWR of better than 2:1 at the output. Full input registers lock in the data at the inputs

Keywords

bipolar integrated circuits; digital integrated circuits; emitter-coupled logic; multiplexing equipment; time division multiplexing; 1.8 W; 100 MHz to 3 GHz; 4:1 time division multiplexer; ECL-level outputs; Hewlett Packard; VSWR; bipolar process; full input registers; fully differential circuit; inverting delay line; off chip drivers; output flip-flop; output retiming; power dissipation; series gated asynchronous multiplexer; travelling wave divider; Bonding; Circuit stability; Clocks; Counting circuits; Delay; Frequency; Multiplexing; Resistors; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51066

Filename

51066