Experiment and simulation of transistor level fault model of IDDT test

Author

Jiang, Shuyan ; Xie, Yongle ; Yu, Dajin ; Luo, Gang

Author_Institution

Sch. of Autom. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2009

fDate

25-27 Sept. 2009

Firstpage

133

Lastpage

137

Abstract

Fault and fault model is the fundament of IC diagnosis. Fault model based on IDDT and its test is the hot issue of modern IC fault diagnosis at present. Open and short fault models of inverter, NAND gate, and SRAM of CMOS technology were built in this paper. In the experiments, we selected the deep sub-micron of 0.18 mum CMOS technology to simulate with HSPICE. The simulations of IDDT waveforms and FFT transform waveforms of different fault models were made and the results were indicated that the IDDT test method can detect the open and short fault of CMOS devices effectively.

Keywords

CMOS integrated circuits; fast Fourier transforms; fault simulation; integrated circuit testing; transistors; waveform analysis; CMOS technology; FFT transform waveforms; IC diagnosis; IDDT test; IDDT waveforms; transistor level fault model; CMOS technology; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Integrated circuit modeling; Integrated circuit testing; Logic testing; Semiconductor device modeling; Voltage; COMS technology; HSPICE; IDDT; fault mode;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Superconductivity and Electromagnetic Devices, 2009. ASEMD 2009. International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-3686-6

Electronic_ISBN

978-1-4244-3687-3

Type

conf

DOI

10.1109/ASEMD.2009.5306676

Filename

5306676