DocumentCode
2216732
Title
An improved design of digital calibration arithmetic applied in pipeline ADC
Author
Wei, Jinghe ; Qian, Liming ; Yu, Zongguang ; Yao, Jiannan ; Shi, Longxing
Author_Institution
58th Res. Inst., CETC, Wuxi, China
fYear
2009
fDate
25-27 Sept. 2009
Firstpage
115
Lastpage
118
Abstract
Digital calibration arithmetic becomes more and more widely applied in pipeline ADC with high precision, the structure of pipeline ADC based on digital calibration is commonly 1.5 bit/stage presently. 2 bit/stage, the structure of which has strong superiority in power consumption and chip size, is adopted in this paper after analyzing the advantages and disadvantages of different kinds of structures. An improved digital calibration arithmetic is designed, which has solved the problem of accuracy of calibrating coefficients in present arithmetic and made the calibrated output data more accurate. The result indicates that the improved digital calibration arithmetic makes the system linearity get highly upgraded.
Keywords
analogue-digital conversion; calibration; pipeline arithmetic; power consumption; digital calibration arithmetic; pipeline ADC; power consumption; Calibration; Capacitors; Digital arithmetic; Electromagnetic devices; Energy consumption; Linearity; Operational amplifiers; Pipelines; Superconductivity; Voltage; 2bit/stage; improved digital calibration arithmetic; linearity; pipeline ADC;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Superconductivity and Electromagnetic Devices, 2009. ASEMD 2009. International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-3686-6
Electronic_ISBN
978-1-4244-3687-3
Type
conf
DOI
10.1109/ASEMD.2009.5306679
Filename
5306679
Link To Document