Title :
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications
Author :
Wang, Zhong ; Kirkpatrick, Michael ; Sha, Edwin Hsing-Mean
Author_Institution :
University of Notre Dame
Keywords :
Central Processing Unit; Computer architecture; Delay; Digital signal processing; Memory management; Modems; Partitioning algorithms; Prefetching; Processor scheduling; Scheduling algorithm;
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
DOI :
10.1109/DAC.2000.855370
