Pseudo-isochronous cell switching in ATM networks

This paper shows how to design an ATM network, for real-time traffic, such that under full network load (i) the maximum delay of a low-rate voice connection is minimized, (ii) the delay uncertainty or jitter is a fixed network parameter, and (iii) the required buffer sizes (inside the network) to ensure loss-free routing is minimized. In addition, this design does not exclude the integration of other classes of traffic, such as connectionless, which have lower priority. The isochronous timing information is used only for regulating and pacing the traffic forwarded inside the network rather than for routing as in traditional circuit switching networks. This means that an ATM cell is sent from one switch to another not at a very specific time but within a time frame of a relatively long duration as compared to the cell transmission time. The routing of cells of each connection is based on VCI and VPI, and as a result, timing errors do not affect the ATM routing. Analytical and simulation results are presented, which demonstrate the effectiveness of this switching approach