Title :
Minflotransit: min-cost flow based transistor sizing tool
Author :
Sundararajan, Kjay ; Sapatnekar, Sachin S. ; Parhi, Keshab K.
Author_Institution :
University of Minnesota
Keywords :
Circuit simulation; Combinational circuits; Costs; Delay; Inverters; MOSFETs; Permission; Runtime; Very large scale integration; Wires;
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
DOI :
10.1109/DAC.2000.855394
