Study on charge trap layer in nanocrystal charge trap MOSFET

Author

Cho, Seung Su ; Joo, Kyong Hee ; Yeo, In-Seok ; Chung, Ilsub

Author_Institution

Sch. of Inf. & commun. Eng., Sungkyunkwan Univ., Suwon

Volume

1

fYear

2006

fDate

22-25 Oct. 2006

Firstpage

696

Lastpage

697

Abstract

In this study, we have investigated the performance two types of nonvolatile MOSFET devices in terms of the performance and reliability. Either SRO (Silicon Rich Oxide) or SRON (Silicon Rich OxyNitride) trap layer was used as a charge trap layer. The trap layers were deposited using ALD (Atomic Layer Deposition) method. The transistor with SRON trap layer combined with thinner tunneling oxide yields larger memory window but worse retention characteristics.

Keywords

MOSFET; atomic layer deposition; nanoelectronics; silicon; tunnelling; ALD; SRO; SRON; atomic layer deposition method; charge trap layer; nanocrystal charge trap MOSFET; silicon rich oxide; silicon rich oxynitride; transistor; trap layers; tunneling oxide; Atomic layer deposition; Dielectrics; Electron traps; Flash memory; MOSFET circuits; Nanocrystals; Nonvolatile memory; Silicon; Threshold voltage; Tunneling; High-k dielectric; Nanocrystal; Nonvolatile Memory; Silicon Rich Oxide; Silicon Rich Oxynitride;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE

Conference_Location

Gyeongju

Print_ISBN

978-1-4244-0540-4

Electronic_ISBN

978-1-4244-0541-1

Type

conf

DOI

10.1109/NMDC.2006.4388966

Filename

4388966