DocumentCode :
2217756
Title :
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
Author :
Katagiri, Hisaaki ; Yasumoto, Keiichi ; Kitajima, Akira ; Ashino, Teruo Hi-n ; Taniguchi, Kazuhiro
Author_Institution :
Osaka Univ.
fYear :
2000
fDate :
2000
Firstpage :
762
Lastpage :
767
Keywords :
Access protocols; Circuit synthesis; Clocks; Combinational circuits; Costs; Hardware; Job design; Network synthesis; Permission; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
Type :
conf
DOI :
10.1109/DAC.2000.855416
Filename :
855416
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2217756